1. Field of Invention
The present invention relates to a bidirectional signal transmission circuit device, and more particularly to a bidirectional current-mode transceiver for improving transmission rates on a transmission line in a manner of current signal transmission.
2. Related Art
In the design of a very-large-scale integrated circuit VLSI, the main factors causing time delay are two kinds, in which one case relates to a logic gate causing the time delay and the other relates to a transmission line causing the delay time. In general, the delay of the logic gate is the major factor that causes time delay. However, due to progress in VLSI processes and the trend of system-on-chip SOC integration, the logic gate delay is reduced along with the scale down of the dimension of device. While the transmission line inside the IC is prolonged with the enlargement of the IC. The progress in the process and the narrowing of the line width of the interconnect cause a greater transmission line delay, thus the delay time of the whole chip is under control of the transmission line delay. Besides, with the increase of the system clock, the delay caused by the transmission line will be greater than that caused by the logic gate.
The reason for the delay caused by the transmission line lies in the effect of the resistance R and capacitance C parasitized on the transmission line delay time=R×C. For the cross-section of the transmission line, the progress in the process at present relates to significantly scaling down the dimension along the horizontal axis only, and according to this process, only slight alterations can be made along the perpendicular dimension. Besides, with the reduction of the distance between the line width of the transmission line and the interconnect, the length-width proportion of the cross-section of the transmission line is increased, and the parasitic resistance on the transmission line cannot be avoided. Moreover, the reduction in the distance between transmission lines may also cause an increase of an adjacent capacitance and a side capacitance.
The method for improving the delay caused by transmission line in conventional technologies can be divided into improvement of the process and improvement by using circuit techniques. For the process, copper processing and low dielectric constant processing are employed to improve the actual resistance and capacitance of the interconnect. For the circuit techniques, buffers are added in the interconnect, and receiving units are added at the terminal of the transmission line to reduce the time delay caused by the transmission line, thereby reducing the transmission line delay.
Then, along with the continuous progress in the process, the area of the chip is reduced, but the package technology of the chip is not improved proportionally. Therefore, the number of the input/output pins and the ratio of the input/output bandwidth required by the whole chip are slightly increased. As a result, each pin should have a large bandwidth to meet the requirement of the signal transmission in the chip. Conventional signal transmission methods include a single-ended signal transmission and a bidirectional signal transmission. Both transmission methods allow each pin in the chip to have a large bandwidth.
Referring to FIG. 1, the circuit architecture of a conventional signal-ended signal transmission is disclosed, wherein a reverser is used to push signals towards the other end of the transmission line, and another reverser is used to receive the signal. In circuit operation, the signals on the transmission line must be of full swing; otherwise, transmission errors are likely to happen. With respect to the power consumption, as the signals are of full swing, the power consumption is large. Besides, due to the full swing of the signals, great signal delay is caused in the rise delay and fall delay.
Referring to FIG. 2, the circuit architecture of a conventional level converter CLC is disclosed. The circuit architecture can convert signals with reduced swings into full-swing signals at the receiving unit. The disadvantage of the circuit architecture is that two supply voltages VDDH, VDDL are required. When the supply voltage VDDL drops to some extent, the circuit cannot operate normally and the delay of the signal transmission will also be increased accordingly.
Referring to FIG. 3, the circuit architecture of a conventional symmetric level converter SLC is disclosed. The circuit architecture requires three supply voltages VDD, VCL, and VSL. Two additional supply voltages VCL and VSL limit the swing on the transmission line. And two transistors of low critical voltage are desired to increase the operating speed of the SLC. As a result, a special process is adopted to achieve the object, resulting in an increase of the cost of the chip.
Referring to FIG. 4, the circuit architecture of a conventional symmetric source follower driver with level converter SSDLC is disclosed. The circuit architecture can overcome the disadvantage of employing two transistors of low critical voltage to improve the operating speed as illustrated above in FIG. 3. However, the use of the symmetric source follower driver SSD may limit the swing range on the transmission line. And as the driving force of the SSD is inadequate, it requires a large-size transistor when pushing a long transmission line.
Referring to FIG. 5, the circuit architecture of a conventional asymmetric source follower driver with level converter ASDLC is disclosed. However, the asymmetric source follower driver ASD may still limit the swing range on the transmission line.
Referring to FIG. 6, the architecture of a convention single-ended current-mode circuit is disclosed, which can provide a strong driving force during the signal conversion, thus reducing the delay time of the interconnect. When no signal is converted, a driving circuit of low swing is used to save power. In the circuit architecture, the input end of the receiver is virtually grounded, so the receiving signal is easily interfered by noises, resulting in circuit operating errors.
Referring to FIG. 7, the architecture of a conventional pulse wave current-mode circuit is disclosed. The circuit architecture allows the signal received to the output point by means of current duplication, and has a low quiescent current. However, the width of the pulse wave may generate parasitic resistance and parasitic capacitance effects on the transmission line due to various lengths and widths of the transmission line. Therefore, the pulse wave width of the signal cannot be too small.
The bidirectional signal transmission mode is a method for multiplying the amount of data transmitted between chips. For the signal transmission between chips, the size of the termination resistor is exact. However, for the signal transmission on chips, the size of the termination resistor is not so exact due to process drift, thus the design of signal transmission on chips is not suitable.
Referring to FIG. 8, the architecture of a first conventional bidirectional signal circuit is disclosed; wherein double drivers are required to perform signal comparison, thus causing large power consumption. Besides, as the two drivers require different impedance matches, it is very difficult in practice.
Referring to FIG. 9, the architecture of a conventional mixed-signal mode bidirectional signal input/output circuit is disclosed. When the input signal is an alternating current AC signal, the impedance on the transmission line is connected in parallel with the impedance at the other transmission end, so the input differential pair impedance matches the transmission line. When a direct current (DC) signal is transmitted, a receiving unit will make an offset error. Therefore, transistors must be added in the circuit to correct the offset error. Besides, the voltage level at the output end of the transmission unit is close to the supply voltage, so the swing voltage can be reduced in an AC operation.
Referring to FIG. 10, the circuit architecture of the receiving end of a conventional bidirectional transmission circuit is disclosed. In the circuit architecture, too many transistor devices are cascaded, so it cannot be applied in a deep sub-micrometer process. Besides, the design of the circuit architecture can only be adopted when the impedance is known, so it can only be applied to the transmission interface between chips, instead of the transmission in chips.
Referring to FIG. 11, the architecture of a conventional point-to-point bidirectional transmission circuit on a current-sensing chip is disclosed. Since a pulldown N-type transistor should provide a path with low resistance, the dimension of the N-type transistor should be large, while a pullup P-type transistor recharges the transmission line, so as to reduce the interference caused by noises. Besides, the latch at the output end discharges the output end via the delay line.
However, in the aforementioned single-ended or bidirectional signal transmission circuit architecture, the parasitic capacitance on the transmission line may be increased with the prolonging of the transmission line, and data transmission rates may be significantly decreased. Therefore, the current-mode signal transmission on chips is applicable for the transmission of a long transmission line.
As such, a current-mode signal transmission circuit is desired to overcome the shortcomings of the prior art.